The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode formed over a semiconductive substrate, and spaced apart source and drain electrodes within the substrate between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductive substrate between the source and drain electrodes. Dielectric materials, such as silicon dioxide, are commonly employed to electrically separate the various gate electrodes in the IC.
One problem with the silicon dioxide-based dielectric materials, however, is that their dielectric constant is relatively high, being approximately 3.9 or higher, depending on factors such as residual moisture content. As a result, the capacitance between the conductive layers in the IC is also relatively high, which in turn limits the speed (frequency) at which a circuit can operate. Strategies being developed to increase the frequency at which the circuit can operate include (1) incorporating metals with lower resistivity values (e.g., copper), and (2) providing electrical isolation with insulating materials having lower dielectric constants relative to silicon dioxide.
One way to fabricate copper structures, such as planar copper circuit paths (or “traces”), on a dielectric substrate is referred to as the “damascene” process. In accordance with this process, the silicon dioxide dielectric surface is patterned by a conventional dry etch process to form holes (i.e., vias) and trenches for vertical and horizontal interconnects prior to deposition of copper onto the surface. Copper has the property of being a fast diffuser during the thermal cycling that a semiconductor substrate experiences during the fabrication process, as well as during actual device operation under applied electric fields, and can move quickly through the underlying dielectric layer and overlying interlevel dielectric (ILD) layers to “poison” the device. Copper diffusion through the substrate dielectric material results in current leakage between adjacent metal lines, leading to degraded device characteristics and, potentially, non-functioning devices. Thus, a diffusion barrier layer is typically deposited in vias and trenches before the deposition of copper. The diffusion barrier layer is provided with a copper seed layer and then over-coated with a copper layer from a copper plating bath. Chemical-mechanical polishing is employed to reduce the thickness of the copper overburden outside the vias and trenches, as well as the thickness of the diffusion barrier layer, until a planar surface that exposes elevated portions of the dielectric surface is obtained. The vias and trenches remain filled with electrically conductive copper forming the circuit interconnects.
Tantalum and tantalum nitride have found wide acceptance in the industry as barrier layer materials and are typically deposited by physical vapor deposition (PVD). However, as the lines defining circuits are being reduced in size, one concern is to avoid degrading the current carrying capacity of the copper lines. As the dimensions of copper lines are reduced, electron scattering from the lines becomes significant and causes an increase in resistivity. One solution is to reduce the thickness of the barrier layer and thereby allow for a proportionately thicker copper line within a given trench by using an atomic layer deposited (ALD) barrier layer. A copper seed layer is then applied by a conventional PVD process. However, formation of the copper seed layer is complicated by the need to provide a precise thickness of the layer to avoid overhang at the top of trenches with overly thick layers and to avoid copper oxidation by atmospheric oxygen occurring with overly thin layers.
One proposed solution is to plate copper directly onto a diffusion barrier layer. Ruthenium, in particular, has shown promise in this application. The electrical conductivity of ruthenium allows for direct plating of copper onto the ruthenium, which obviates the need for a copper seed layer. Although the possibility of replacing tantalum/tantalum nitride barriers layers with ruthenium remains an attractive possibility, the likely course of development appears to lie with a copper-ruthenium-tantalum/tantalum nitride system.
FIG. 1 is illustrative of such a system. As shown, a dielectric material layer 101, such as a layer of organosilicate glass (also called carbon-doped oxide or SiCOH), has a trench and/or via 110 formed therein. As noted above, the via 110 may be formed by patterning and etching the dielectric layer 101. A hardmask layer 102 is used to protect areas of the dielectric layer that are not etched. A layer of a first diffusion barrier material 103, such as tantalum or tantalum nitride, is deposited within the via 110 and over the hardmask layer 102. A layer of a second diffusion barrier material 104, which also has compatibility for the direct plating of copper thereto, such as ruthenium, is deposited over the first diffusion barrier material 103. Subsequently, a copper interconnect 105 is plated over the second diffusion barrier material 104 and within the via 110.
After the plating of the copper interconnect, it is typically necessary to polish or etch the substrate so as to planarize the diffusion barrier material layers 103, 104 and the copper interconnect 105 to the level of the hardmask 102. Polishing compositions that have been developed for ruthenium and other noble metals typically contain strong oxidizing agents, have a low pH, or both. Copper tends to oxidize very rapidly in these polishing compositions. Additionally, because of the difference in standard reduction potentials of ruthenium and copper, copper suffers from galvanic attack by ruthenium in the presence of conventional ruthenium polishing compositions. The galvanic attack leads to etching of copper lines and a resulting degradation of circuit performance. Further, the wide difference in chemical reactivity of copper and ruthenium in conventional polishing compositions results in widely differing rates of removal in chemical-mechanical polishing of substrates containing both metals, which can result in overpolishing of copper during ruthenium barrier polishing.
This effect is illustrated in FIGS. 2 and 3. With reference to FIG. 2, the copper interconnect 105 may first be planarized to the level of the second diffusion barrier (ruthenium) layer 104 using convention CMP techniques. Wet etching could be employed to reduce the diffusion barrier layers 103, 104 and the copper interconnect 105 to the level of the hardmask 102, as shown in FIG. 3. However, due to the above-noted rapid oxidation of copper, the galvanic attack by ruthenium, and the difference in reactivity between the various metals of layer 103 through 105, the copper interconnect becomes over-etched, resulting in a void region 111 formed within the trench 110.
Substrates including tantalum or tantalum nitride in addition to ruthenium and copper pose additional challenges in that polishing compositions suitable for ruthenium or copper, themselves highly dissimilar materials, are typically unsuitable for the polishing of tantalum or tantalum nitride layers. Polishing compositions suitable for use in the polishing of tantalum or tantalum nitride barrier layers tend to chemically attack copper remaining in the circuit lines, which can lead to dishing of the circuit lines. Dishing of circuit lines can lead to discontinuities in the circuits and to non-planarity of the substrate surface, as shown in FIG. 3, complicating further processing steps. Successful implementation of ruthenium-copper-tantalum microelectronic technology will thus require new polishing and/or etching methods suitable for the polishing and/or etching of all three materials.
Accordingly, it is desirable to provide improved methods for fabricating integrated circuits using damascene process flows. Additionally, it is desirable to provide such methods that prevent over-etching of copper interconnects. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.